This invention relates generally to alternative sensing schemes for a ferroelectric memory cell.
The basic configuration 10 of a ferroelectric memory cell 12 is shown in FIG. 1. FIG. 1 includes a one-transistor, one-capacitor memory cell 12 that includes an MOS transistor 14 labeled M1, and a ferroelectric capacitor 16 labeled C.sub.Cell, which are coupled together at internal cell node 15. Ferroelectric memory cell 12 is a three terminal device in which one end of ferroelectric capacitor 16 is coupled to an active plate line 18, thee gate of transistor 14 is coupled to a word line 20, and the source/drain of transistor 14 is coupled to a bit line 22. Bit line 22 is also coupled to a sense amplifier 26. Sense amplifier 26 receives a reference voltage, VR, at node 28, and an enable signal, SAE, at node 30. The reference voltage, VR, is selected to be about halfway between the voltage developed in response to a logic zero state on bit line 22 and the voltage developed in response to a logic one state on bit line 22. In the prior art sensing schemes, bit line 22 is usually "pre-charged" to ground voltage (zero volts). Sense amplifier 26 resolves the difference in voltages (or charge) found on bit line 22 and the reference voltage node 28 into a full logic voltage on bit line 22, usually five volts or ground voltage. The enable signal at node 30 turns on circuitry in sense amplifier 26 to effect the voltage comparison. Memory cell 12 is typically part of a memory array that is not shown in FIG. 1, arranged in rows and columns.
Memory cell 12 can also be a complementary two-transistor, two capacitor memory cell coupled to a differential bit line (not shown in FIG. 1). In this case, reference voltage VR is not used, and node 28 is connected to a complementary bit line of the memory cell.
A first prior art sensing scheme known as "up down" sensing is illustrated in FIGS. 2A and 2B. FIG. 2A includes a timing diagram of ferroelectric memory cell 12 having a logic one data state. In ferroelectric memories, the data state is determined by the polarization vector of the ferroelectric material used in capacitor 16. The timing diagram of FIG. 2A includes the word line (WL), plate line (PL), and bit line (BL) waveforms. Also included in FIG. 2A is a corresponding hysteresis loop diagram illustrating the polarization states of ferroelectric capacitor 16. As is known in the art, the x-axis of the hysteresis loop represents the applied voltage (V) across the ferroelectric capacitor, whereas the y-axis of the hysteresis loop represents the polarization or charge (Q) associated with the ferroelectric capacitor. The timing diagram of FIG. 2A is labeled at various points in time labeled t1 through t7. These same timing labels are used on the corresponding hysteresis loop diagram to illustrate the behavior of ferroelectric memory cell 12 during the up-down sensing scheme.
At an initial time t1, the word, plate, and bit lines of ferroelectric memory cell 12 are all set to zero volts. At the initial time t1, memory cell 12 is in a logic one state, which is also illustrated on the corresponding hysteresis diagram. By convention, point t1 is located on the negative "Q" axis to represent the logic one state of memory cell 12. At time t2, word line 20 is stepped from the initial logic zero voltage to a logic one voltage, usually five volts. Only changing the voltage on word line 20 does not change the location of the operating point on the hysteresis diagram, which is also labeled t2. At time t3, the plate line is pulsed to a logic one voltage with a positive-going pulse, and a voltage is developed on bit line 22. The operating point on the hysteresis diagram moves from t1, t2, to t3 (representing a positive applied voltage and a corresponding charge). At time t4, the plate line voltage is returned to the logic zero voltage, with a slight loss of voltage on the bit line. The new operating point is also labeled t4 on the hysteresis diagram. Between times t4 and t5, the sense amplifier signal is energized and the voltage on bit line 22 is resolved into a full logic one voltage, when compared to an appropriately selected reference voltage VR. At time t5, therefore, the voltage on word line 20 is high, the voltage on plate line 18 is low, and the voltage on bit line 22 is high. This operating condition corresponds to a negative voltage being applied across ferroelectric capacitor 16, which is also illustrated and labeled t5 on the hysteresis diagram. At time 16, the plate line is again pulsed with a positive-going pulse, which returns to a logic zero level at time t7. The second plate line pulse is only required if new data is written into memory cell 12 between times t4 and t5. At time t7 the original data state is restored, and linear or "DRAM" charge remains in the cell. Over time, however, the DRAM charge leaks away and the voltage at internal node 15 decays, which restores the original operating point at t1 on the hysteresis loop diagram.
FIG. 2B includes a timing diagram of ferroelectric memory cell 12 having a logic zero data state, again in the up-down sensing mode. The timing diagram of FIG. 2B also includes word line (WL), plate line (PL), and bit line (BL) waveforms. The timing diagram of FIG. 2B includes points in time labeled t1 through t7 that are also used on the corresponding hysteresis loop diagram to illustrate the behavior of ferroelectric memory cell 12 during the up-down sensing scheme.
At an initial time t1, the word, plate, and bit lines of ferroelectric memory cell 12 are again all set to zero volts. At the initial time t1, memory cell 12 is in a logic zero state, which is also illustrated on the corresponding hysteresis diagram. By convention, point t1 is located on the positive Q axis to represent the logic zero state of memory cell 12. At time t2, word line 20 is stepped from the initial logic zero voltage to a logic one voltage, usually five volts. Only changing the voltage on word line 20 does not change the location of the operating point on the hysteresis diagram, which is also labeled t2. At time t3, the plate line is pulsed to a logic one voltage with a positive-going pulse, and a voltage is developed on bit line 22. The operating point on the hysteresis diagram moves from t1, t2, to t3 (again, representing a positive applied voltage and a corresponding charge). At time t4, the plate line voltage is returned to the logic zero voltage, with a corresponding loss of voltage on the bit line. The new operating point is also labeled t4 on the hysteresis diagram. Between times t4 and t5, the sense amplifier signal is energized and the voltage on bit line 22 is resolved into a full logic zero voltage, when compared to an appropriately selected reference voltage VR. At time t5, therefore, the voltage on word line 20 is high, the voltage on plate line 18 is low, and the voltage on bit line 22 is also low. This operating condition corresponds to no voltage being applied across ferroelectric capacitor 16 and the original polarization state, which is also illustrated and labeled t5 on the hysteresis diagram. At time t6, the plate line is again pulsed with a positive-going pulse, which returns to a logic zero level at time t7. The second plate line pulse is only required if new data is written into memory cell 12 between times t4 and t5. At time t7 the original operating point is restored.
A second prior art sensing scheme known as "up only" sensing is illustrated in FIGS. 3A and 3B. FIG. 3A includes a timing diagram of ferroelectric memory cell 12 having a logic one data state. The timing diagram of FIG. 3A includes the word line (WL), plate line (PL), and bit line (BL) waveforms. Also included in FIG. 3A is a corresponding hysteresis loop diagram illustrating the polarization states of ferroelectric capacitor 16. The timing diagram of FIG. 3A is labeled at various points in time labeled t1 through t7. These same timing labels are used on the corresponding hysteresis loop diagram to illustrate the behavior of ferroelectric memory cell 12 during the up only sensing scheme.
At an initial time t1, the word, plate, and bit lines of ferroelectric memory cell 12 are all set to zero volts. At the initial time t1, memory cell 12 is in a logic one state, which is also illustrated on the corresponding hysteresis diagram. By convention, point t1 is located on the negative "Q" axis to represent the logic one state of memory cell 12. At time t2, word line 20 is stepped from the initial logic zero voltage to a logic one voltage, usually five volts. Only changing the voltage on word line 20 does not change the location of the operating point on the hysteresis diagram, which is also labeled t2. At time t3, the plate line is pulsed to a logic one voltage with a positive-going pulse, and a voltage is developed on bit line 22. The operating point on the hysteresis diagram moves from t1, t2, to t3 (representing a positive applied voltage and a corresponding charge). Between times t3 and t4, the sense amplifier signal is energized and the voltage on bit line 22 is resolved into a full logic one voltage, when compared to an appropriately selected reference voltage VR. At time t4, therefore, the voltages on word line 20, plate line 18, and bit line 22 are all high. This operating condition corresponds to a no voltage being applied across ferroelectric capacitor 16, but with a flipped polarization state, which is also illustrated and labeled t4 on the hysteresis diagram. At time t5, the plate line is returned to a logic zero level. The corresponding operating condition is illustrated and labeled t5 on the hysteresis diagram. At time t5 the original data state is restored, and linear or DRAM charge remains in the cell. Over time, however, the DRAM charge leaks away and the voltage at internal node 15 decays, which restores the original operating point at t1 on the hysteresis loop diagram.
FIG. 3B includes a timing diagram of ferroelectric memory cell 12 having a logic zero data state, again in the up only sensing mode. The timing diagram of FIG. 3B also includes word line (WL), plate line (PL), and bit line (BL) waveforms. The timing diagram of FIG. 3B includes points in time labeled t1 through t7 that are also used on the corresponding hysteresis loop diagram to illustrate the behavior of ferroelectric memory cell 12 during the up only sensing scheme.
At an initial time t1, the word, plate, and bit lines of ferroelectric memory cell 12 are again all set to zero volts. At the initial time t1, memory cell 12 is in a logic zero state, which is also illustrated on the corresponding hysteresis diagram. By convention, point t1 is located on the positive Q axis to represent the logic zero state of memory cell 12. At time t2, word line 20 is stepped from the initial logic zero voltage to a logic one voltage, usually five volts. Only changing the voltage on word line 20 does not change the location of the operating point on the hysteresis diagram, which is also labeled t2. At time t3, the plate line is pulsed to a logic one voltage with a positive-going pulse, and a small voltage is developed on bit line 22. The operating point on the hysteresis diagram moves from t1, t2, to t3 (again, representing a positive applied voltage and a corresponding charge). Note that operating point 3 is shown to be not completely saturated, due to the small voltage present on bit line 22. Between times t3 and t4, the sense amplifier signal is energized and the voltage on bit line 22 is resolved into a full logic zero voltage, when compared to an appropriately selected reference voltage VR. At time t4, therefore, the voltage on word line 20 and plate line 18 is high, and the voltage on bit line 22 is low. This operating condition corresponds a full logic voltage being applied across ferroelectric capacitor 16, but with the original polarization state, which is also illustrated and labeled t4 on the hysteresis diagram. At time t5, the plate line is returned to a logic zero level and the original operating point is restored.
The "up down" sensing method of FIGS. 2A and 2B is a robust sensing method in that it is relatively insensitive to the properties of the ferroelectric material used; for example a "compensated" ferroelectric material as is evidenced by a shifting and distortion of the corresponding hysteresis loop. The "up down" sensing method of FIGS. 2A and 2B is relatively slow, however, since the plate line pulse must transition both high and low before the sense amplifier can be energized. The "up only" sensing method of FIGS. 3A and 3B is faster than the "up down" sensing method since only one transition of the plate line is involved, but at the price of a less robust sensing method.
What is desired is an alternative robust sensing method for a ferroelectric memory cell that is faster than the prior art "up down" sensing method.